Knowledge-Driven AI for SystemVerilog Assertions
Ships with downloadable RAG-SVA files.
Indian edition ($38): contact ben_cohen@systemverilog.us
Books
Current titles are available in paper and PDF. Earlier titles include free PDFs and companion code where available.
Fast-Tracking SVA through Exposure
SystemVerilog Assertions Handbook
SystemVerilog Assertions Handbook, 4th Edition in Chinese
Earlier books
- Real Chip Design and Verification Using Verilog and VHDL PDF edition, $3 PDF (Payhip)
- A Pragmatic Approach to VMM Adoption: a SystemVerilog Framework for Testbenches 2007 PDF Code
- Component Design by Example: A Step-by-Step Process Using VHDL with UART as Vehicle Emphasizes requirements and test plans Overview PDF Code (zip) Code (tar)
- Using PSL/Sugar with Verilog and VHDL Two editions, translated to Japanese by Cadence
- VHDL Coding Styles and Methodologies: An In-Depth Tutorial Two editions, 1995 and 1999
- VHDL Answers to Frequently Asked Questions Two editions, evolved from the comp.lang.vhdl forum
Papers
Papers, notes, and reference code, newest first within each topic. Start with Mapping the RAG-SVA Body of Work for a guide to how they fit together.
RAG-SVA and AI-assisted verification
- Mapping the RAG-SVA Body of WorkPDF
- Using RAG-RTL with RAG-SVA: A Pipelined Multiplier ExamplePDF
- Naming Conventions for SystemVerilog Design and SVAPDF
- Testbench Styles Supported by RAG-SVA: Directed, Fast Random, and UVMPDF
- The Value of This Book Without Any Particular AI ToolPDF
- Notes: Is 1800 in LLMs?Notes
- RAG-SVA in the Landscape of LLM-Based Assertion GenerationPDF
- Frame Drift in Multi-Turn LLM Interaction, and Why RAG-SVA Rule Corpora Already Defend Against ItPDF
- And Now Is the Time: How AI with RAG-SVA ...PDF
- What if AI Scribe for Doctors Were Used for AI Scribe for Chip Design and Verification?PDF
- Gen-SVA: Source-Agnostic Generation of Formal-Ready SVAPDF
- RAG-SVA Paradigm Shift in FVPDF
- grnt -> req: Claude LLM vs. Claude LLM + RAGPDF
- AI-Assisted FV of a SystemVerilog Parking Lot ControllerCode + paper (tar.gz)
- OVL Arbiter: Claude with vs. without SVA-RAG for Formal VerificationCode + paper (gz)
- Leveraging Bing GPT-4 for Digital Design and Verification with SystemVerilog and AssertionsPDFRelated: Parking lot with Bing GPT
Formal verification
- Your Chip Moved from 5 nm to 3 nm. Did Your SVA Notice?PDF
- Formal Verification Scope Analysis After a Design ChangePDF
- Notes: Constraint Overhead in Formal VerificationNotes
- Determinism in SystemVerilog Assertions for Formal VerificationPDF
- Async FIFO Decomposition: From RTL and SVA to a Black-Box Specification, and BackPDF
- Deriving a Formal req/ack Assertion Under the RAG-SVA MethodologyPDF
- How to Use the "not" Operator for Formal VerificationPDF
- FV Abstraction Techniques in RAG-SVAPDF
- Degeneracy, Environment vs. Obligation, and Design Intent: A req/ack Case StudyPDF
- Which Assertion Limits Your Clock?PDF
Requirements and methodology
Language conversion
- Converting SV/SVA to VHDL/PSLCode + paper (tar)
- Converting Legacy VHDL to SVA-FV-Ready Code, with SpecsCode + paper (tar)
- Converting Legacy PSL-SIM to SVA-FV-Ready CodeCode + paper (tar.gz)
SVA concepts and tutorials
- Understanding the SVA Engine Using the Fork-Join ModelPDF
- Reflections on Users' Experiences with SVA, Part 1PDF
- Reflections on Users' Experiences with SVA, Part 2PDF
- Understanding Assertion Processing Within a Time StepPDF
- Understanding and Using Immediate AssertionsPDF
- SVA Package: Dynamic and Range Delays and RepeatsLink
- SVA Package: sva_repeat_delay_thru_pkg_011624.svSV source
- Support Logic and the always PropertyPDF
- SVA in a UVM Class-Based EnvironmentPDF
- SVA for Statistical Analysis of a Weighted Work-Conserving Prioritized Round-Robin ArbiterPDFArbiter code (.sv)
- Getting Started with Verification with SystemVerilogPDF
- Understanding SVA DegeneracyPDFAlternate link
- Understanding the within OperatorPDF
- The Traditional Req/Ack Handshake: It's More Complicated Than You Think!PDF
- Dynamic Data Structures in AssertionsPDF
- (intersect) vs. (throughout, until, until_with, within)PDF
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